5P49V5929 Datasheet, PDF (9/27 Pages) Integrated Device Technology – Generates up to four independent output frequencies

5P49V5929 DATASHEET
Output Skew
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100 MHz output
and a 2800 MHz VCO, you can select how many 11.161pS
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Output Drivers
The operating voltage ranges of each output is determined by
its independent output power pin (V_DDO) and thus each can
have different output voltage levels. Output voltage levels of
1.8V, 2.5V, or 3.3V are supported for LVCMOS.
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
LVCMOS Operation
Output pairs OUT1 & OUT2; OUT3 & OUT4; OUT5 & OUT6;
OUT7 & OUT8 each operate the frequency as determined by
corresponding programmed Fractional Output Dividers. All
the previously described configuration and control apply
equally to all outputs. Frequency, phase alignment, voltage
levels and enable / disable status apply to all the OUTx pins.
The outputs can be selected to be phase-aligned with each
other or inverted relative to one another by register
programming bits. Selection of phase-alignment may have
negative effects on the phase noise performance of any part
of the device due to increased simultaneous switching noise
within the device.
Device Hardware Configuration
The 5P49V5929 supports an internal One-Time
Programmable (OTP) memory that can be pre-programmed
at the factory with up to 4 complete device configuration.
These configurations can be over-written using the serial
interface once reset is complete. Any configuration written via
the programming interface needs to be re-written after any
power cycle or reset. Please contact IDT if a specific
factory-programmed configuration is desired.
Device Start-up & Reset Behavior
The 5P49V5929 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers using the configuration
stored in the internal One-Time Programmable (OTP)
memory.
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
Power Up Ramp Sequence
VDDA and VDDD must ramp up together. VDDO0~4 must
ramp up before, or concurrently with, VDDA and VDDD. All
power supply pins must be connected to a power rail even if
the output is unused. All power supplies must ramp in a linear
fashion and ramp monotonically.
VDDO0~4
VDDA
VDDD
REVISION B 07/13/15
9
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