5P49V5929 Datasheet, PDF (17/27 Pages) Integrated Device Technology – Generates up to four independent output frequencies

5P49V5929 DATASHEET
Symbol
Parameter
Test Conditions
Min. Typ. Max.
t6
Clock Jitter
Cycle-to-Cycle jitter (Peak-to-Peak), multiple
74
output frequencies switching, LVCMOS outputs
(1.8 to 3.3V nominal output voltage)
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 5MHz integration
0.5
range) reference clock (OUT0),
25 MHz LVCMOS outputs (1.8 to 3.3V nominal
output voltage).
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
RMS Phase Jitter (12kHz to 20MHz integration
range) LVCMOS output, VDDO = 3.465V, 25MHz
crystal, 156.25MHz output frequency
OUT0=25MHz
OUT1=100MHz
OUT2=125MHz
OUT3=156.25MHz
0.75 1.5
t7
Output Skew
t8 ³ Startup Time
t9 ⁴ Startup Time
Skew between the same frequencies, with outputs
using the same driver format and phase delay set
to 0ns.
PLL lock time from power-up, measured after
all VDD's have raised above 90% of their
target value.
PLL lock time from shutdown mode
75
10
3
4
1. Practical lower frequency is determined by loop filter settings.
2. A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3. Includes loading the configuration bits from memory to PLL registers. It does not include memory programming/write time.
4. Actual PLL lock time depends on the loop configuration.
Units
ps
ps
ps
ps
ms
ms
Table 18:Spread Spectrum Generation Specifications
Symbol Parameter
f_OUT
f_MOD
f_SPREAD
Output Frequency
Mod Frequency
Spread Value
Description
Output Frequency Range
Modulation Frequency
Amount of Spread Value (programmable) - Center Spread
Amount of Spread Value (programmable) - Down Spread
Min Typ Max
5
300
30 to 63
±0.25% to ±2.5%
-0.5% to -5%
Unit
MHz
kHz
%f_OUT
REVISION B 07/13/15
17
PROGRAMMABLE CLOCK GENERATOR