IDT70V7278S Datasheet, PDF (8/16 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects
Industrial and Commercial Temperature Ranges
Assigning the Banks via the
External Bank Selects
There are four bank select pins available on the IDT70V7278, and
each of these pins is associated with a specific bank within the memory
array. The pins are user-controlled inputs: access to a specific bank is
assigned to a particular port by setting the input to the appropriate
level. The process of assigning the banks is detailed in Truth Table IV.
Once a bank is assigned to a port, the owning port has full access to
read and write within that bank. The opposite port is unable to access
that bank until the user reassigns the port. Access by a port to a bank
which it does not control will have no effect if written, and if read
unknown values on D0-D15 will be returned. Each port can be assigned
as many banks within the array as needed, up to and including all four
banks.
The bank select pin inputs must be set at either VIH or VIL - these
inputs are not tri-statable. When changing the bank assignments,
accesses of the affected banks must be suspended. Accesses may
continue uninterrupted in banks that are not being reallocated.
Truth Table IV – Memory Bank
Assignment (CE = VIH)^(2,3)
OR _{BKSEL0 BKSEL1 BKSEL2 BKSEL3}
BANK AND
DIRECTION⁽¹⁾
F _H
X
X
X
BANK 0 LEFT
X
H
X
X
BANK 1 LEFT
D _X
X
H
X
BANK 2 LEFT
E _X
X
X
H
BANK 3 LEFT
D _L
X
X
X
BANK 0 RIGHT
N ^S _X
L
X
X
BANK 1 RIGHT
E ^N _X
X
L
X
BANK 2 RIGHT
M _IG X
X
X
L
BANK 3 RIGHT
NOTES:
4078 tbl 13
M ^S _{1. Bank 0 refers to the first 8Kx16 memory spaces, Bank 1 to the second 8Kx16}
O ^{E memory spaces, Bank 2 to the third 8Kx16 memory spaces, and Bank 3 to the}
fourth 8Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left port;
C ^{D 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks may be}
assigned to either port.
2. The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-
E _{statable. When changing the bank assignments, accesses of the affected banks}
R ^{W must be suspended. Accesses may continued uninterrupted in banks that are not}
being reallocated.
E _{3. 'H' = VIH, 'L' = VIL, 'X' = Don't Care.}
OT ^N _{Mailbox Interrupts and Interrupt}
N ^{Control Registers}
If the user chooses the mailbox interrupt function, four mailbox masked via software. Masking of the interrupt sources is done in the
locations are assigned to each port. These mailbox locations are Mask Register. The masks are individual and independent: a port can
external to the memory array. The mailboxes are accessed by taking mask any combination of interrupt sources with no effect on the other
MBSEL LOW while holding CE HIGH.
sources. Each port can modify only its own Mask Register. The use of
The mailboxes are 16 bits wide and controllable by byte: this register is detailed in Truth Table V.
the message is user-defined since these are addressable SRAM
Two registers are provided to permit interpretation of interrupts:
locations. An interrupt is generated to the opposite port upon writing to these are the Interrupt Cause Register and the Interrupt Status
the upper byte of any mailbox location. A port can read the message Register. The Interrupt Cause Register gives the user a snapshot of
it has just written in order to verify it: this read will not alter the status what has caused the interrupt to be generated - the specific mailbox
of the interrupt sent to the opposite port. The interrupted port can clear written to by the opposite port. The information in this register provides
the interrupt by reading the upper byte of the applicable mailbox. This post-mask signals: interrupt sources that have been masked will not
read will not alter the contents of the mailbox. The use of mailboxes to be updated. The Interrupt Status Register gives the user the status of
generate interrupts to the opposite port and the reading of mailboxes all bits that could potentially cause an interrupt regardless of whether
to clear interrupts is detailed in Truth Table V.
they have been masked. The use of the Interrupt Cause Register and
If desired, any of the mailbox interrupts can be independently the Interrupt Status Register is detailed in Truth Table V.
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