IDT70V7278S Datasheet, PDF (1/16 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 32K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS

HIGH-SPEED 3.3V
32K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
IDT70V7278S/L
Features
◆ _{32K x 16 Bank-Switchable Dual-Ported SRAM Architecture}
– Four independent 8K x 16 banks
– 512 kilobit of memory on chip
◆ _{Fast asynchronous address-to-data access time: 15ns}
◆ _{User-controlled input pins included for bank selects}
◆ _{Independent port controls with asynchronous address &}
data busses
◆ _{Four 16-bit mailboxes available to each port for inter-}
processor communications; interrupt option
◆ _{Interrupt flags with programmable masking}
◆ _{Dual Chip Enables allow for depth expansion without}
external logic
◆ _{UB and LB are available for x8 or x16 bus matching}
◆ _{LVTTL-compatible, single 3.3V (±5%) power supply}
◆ _{Available in a 100-pin Thin Quad Flatpack}
◆ _{Industrial temperature range (-40° to +85°C) is available}
for selected speeds
Functional Block Diagram
R _R/WL
O _CE0L
CE1L
F _UBL
LBL
OEL
CONTROL
LOGIC
ED _I/O8L-15L
I/O0L-7L
I/O
CONTROL
END ^{NS A12L}
A0L(1)
ADDRESS
DECODE
MM ^{SIG BA1L}
BA0L
BANK
DECODE
RECEOW ^DE _BKSEL3(2)
NOT ^{N BKSEL0(2)}
BANK
SELECT
A5L(1)
A0L(1)
LBL/UBL
MUX
8Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
8Kx16
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx16
MEMORY
ARRAY
(BANK 3)
MUX
MAILBOX
INTERRUPT
CONTROL
LOGIC
I/O
CONTROL
ADDRESS
DECODE
BANK
DECODE
A5R(1)
A0R(1)
LBR/UBR
R/WR
CE0R
CE1R
UBR
LBR
OER
I/O8R-15R
I/O0R-7R
A12R
A0R(1)
BA1R
BA0R
OEL
LOGIC
OER
R/WL
R/WR
MBSELL
INTL
CEL
CER
MBSELR
INTR
,
4078 drw 01
NOTES:
1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox
address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.
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©2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4078/7