IDT709279 Datasheet, PDF (8/18 Pages) Integrated Device Technology – HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)^(3,4) (VCC = 5V ± 10%, TA = 0°C to +70°C)
709279/69X6
Com'l Only
709279/69X7
Com'l Only
709279/69X9
Com'l Only
709279/69X12
Com'l
& Ind
709279/69X15
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCYC1
Clock Cycle Time (Flow-Through)⁽²⁾
19
____
22
____
25
____
30
____
35
____
ns
tCYC2
Clock Cycle Time (Pipelined)⁽²⁾
tCH1
Clock High Time (Flow-Through)⁽²⁾
tCL1
Clock Low Time (Flow-Through)⁽²⁾
10
____
12
____
15
____
20
____
25
____
ns
6.5
____
7.5
____
12
____
12
____
12
____
ns
6.5
____
7.5
____
12
____
12
____
12
____
ns
tCH2
Clock High Time (Pipelined)⁽²⁾
4
____
5
____
6
____
8
____
10
____
ns
tCL2
Clock Low Time (Pipelined)⁽²⁾
4
____
5
____
6
____
8
____
10
____
ns
tR
Clock Rise Time
____
3
____
3
____
3
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
____
3
____
3
____
3
ns
tSA
Address Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHA
Address Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSC
Chip Enable Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHC
Chip Enable Hold Time
tSW
R/W Setup Time
tHW
R/W Hold Time
0
____
0
____
1
____
1
____
1
____
ns
3.5
____
4
____
4
____
4
____
4
____
ns
0
____
0
____
1
____
1
____
1
____
ns
tSD
Input Data Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHD
Input Data Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSAD
ADS Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHAD
ADS Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSCN
CNTEN Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHCN
CNTEN Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tSRST
CNTRST Setup Time
3.5
____
4
____
4
____
4
____
4
____
ns
tHRST
CNTRST Hold Time
0
____
0
____
1
____
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
6.5
____
7.5
____
9
____
12
____
15
ns
tOLZ
Output Enable to Output Low-Z⁽¹⁾
tOHZ
Output Enable to Output High-Z⁽¹⁾
2
____
2
____
2
____
2
____
2
____
ns
1
7
1
7
1
7
1
7
1
7
ns
tCD1
Clock to Data Valid (Flow-Through)⁽²⁾
tCD2
Clock to Data Valid (Pipelined)⁽²⁾
____
15
____
18
____
20
____
25
____
30
ns
____
6.5
____
7.5
____
9
____
12
____
15
ns
tDC
Data Output Hold After Clock High
tCKHZ
Clock High to Output High-Z⁽¹⁾
2
____
2
____
2
____
2
____
2
____
ns
2
9
2
9
2
9
2
9
2
9
ns
tCKLZ
Clock High to Output Low-Z⁽¹⁾
2
____
2
____
2
____
2
____
2
____
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
24
____
28
____
35
____
40
____
50
ns
tCCS
Clock-to-Clock Setup Time
____
9
____
10
____
15
____
15
____
20
ns
NOTES:
3243 tbl 11
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-
tion, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC
signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.482