IDT709279 Datasheet, PDF (1/18 Pages) Integrated Device Technology – HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM

HIGH-SPEED 32/16K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT709279/69S/L
Features
◆ _{True Dual-Ported memory cells which allow simultaneous}
access of the same memory location
◆ _{High-speed clock to data access}
– Commercial: 6.5/7.5/9/12/15ns (max.)
– Industrial: 12ns (max.)
◆ _{Low-power operation}
– IDT709279/69S
Active: 950mW (typ.)
Standby: 5mW (typ.)
– IDT709279/69L
Active: 950mW (typ.)
Standby: 1mW (typ.)
◆ _{Flow-Through or Pipelined output mode on either port via}
the FT/PIPE pin
◆ _{Counter enable and reset features}
◆ _{Dual chip enables allow for depth expansion without}
additional logic
◆ _{Full synchronous operation on both ports}
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
◆ _{Separate upper-byte and lower-byte controls for}
multiplexed bus and bus matching compatibility
◆ _{TTL- compatible, single 5V (±10%) power supply}
◆ _{Industrial temperature range (–40°C to +85°C) is}
available for selected speeds
◆ _{Available in a 100-pin Thin Quad Flatpack (TQFP) package}
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
1
0
0/1
LBL
OEL
R/WR
UBR
CE0R
1
CE1R
0
0/1
LBR
OER
FT/PIPEL
I/O8L-
I/O15L
I/O0L-I/O7L
0/1 ^{1b 0b} b a ^{1a 0a}
A14L⁽¹⁾
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
0a 1a _{a b0b} 1b _0/1
Counter/
Address
Reg.
NOTE:
1. A14X is a NC for IDT709269.
1
©2004 Integrated Device Technology, Inc.
FT/PIPER
I/O8R-I/O15R ^{, ,}
I/O0R-I/O7R
A14R⁽¹⁾
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3243 drw 01
JUNE 2004
DSC-3243/13