ICS8624I Datasheet, PDF (8/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

ICS8624I
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
HSTL OUTPUT
All unused HSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LAYOUT GUIDELINE
The schematic of the ICS8624I layout example is shown in
Figure 3A. The ICS8624I recommended PCB board layout for
this example is shown in Figure 3B. This layout example is
used as a general guideline. The layout in the actual system
will depend on the selected component types, the density of
the components, the density of the traces, and the stack up
of the P.C. board.
VDD
SP = Space (i.e. not intstalled)
R7
VDD
VDDA
RU2 RU3 RU4 RU5
SP
1K
1K
SP
10
VDD=3.3V
C11
0.01u
C16
CLK_SEL
VDDO=1.8V
10u
PLL_SEL
SEL0
SEL1
DIV_SEL[1:0] = 01
155.5 MHz
Zo = 50 Ohm
+
RD2
1K
RD3
SP
RD4
SP
RD5
1K
VDD
VDDO
Zo = 50 Ohm
-
LVHSTL_input
3.3V
(155.5 MHz)
SEL0
Zo = 50 Ohm
SEL1
Zo = 50 Ohm
3.3V PECL Driver
CLK_SEL
R8
R9
50
50
U1
1
2
3
4
5
6
SEL0
SEL1
CLK0
nCLK0
CLK1
7 ^nCLK2
8
CLK_SEL
MR
8624
VDDO
Q3
nQ3
Q2
nQ2
24
23
22
21
20
19
Q1 ₁₈
nQ1
VDDO
17
R4A R4B
50
50
Bypass capacitor located near the power pins
(U1-9) VDD (U1-32)
C1
0.1uF
C6
0.1uF
R10
(U1-16) VDDO (U1-17) (U1-24) (U1-25)
50
R2B
R2A
50
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
8624BYI
FIGURE 3A. ICS8624I HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
www.idt.com
8
REV. C JULY 30, 2010