ICS8624I Datasheet, PDF (1/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

ICS8624I
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS8624I is a high performance, 1-to-5
Differential-to-HSTL zero delay buffer. The ICS8624I
has two selectable clock input pairs. The CLK0,
nCLK0 and CLK1, nCLK1 pair can accept most standard
differential input levels. The VCO operates at a frequency
range of 250MHz to 630MHz. Utilizing one of the outputs
as feedback to the PLL, output frequencies up to 630MHz
can be regenerated with zero delay with respect to the
input. Dual reference clock inputs support reduntant clock
or multiple reference applications..
FEATURES
• Fully integrated PLL
• Five differential HSTL compatible outputs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 630MHz
• Input frequency range: 31.25MHz to 630MHz
• VCO range: 250MHz to 630MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 35ps (maximum)
• Output skew: 50ps (maximum)
• Static phase offset: 30ps ±125ps
• 3.3V core, 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PLL_SEL
CLK0
nCLK0
0
CLK1
1
nCLK1
CLK_SEL
FB_IN
nFB_IN
÷4, ÷8
0
1
PLL
SEL0
SEL1
MR
8624BYI
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
SEL0
32 31 30 29 28 27 26 25
1
24
VDDO
Q3
nQ3
SEL1 2
CLK0 3
23 Q3
22 nQ3
Q4
nQ4
nCLK0 4
CLK1 5
ICS8624I
21 Q2
20 nQ2
nCLK1 6
19 Q1
CLK_SEL 7
18 nQ1
MR 8
1 7 VDDO
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
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1
REV. C JULY 30, 2010