ICS853017 Datasheet, PDF (8/15 Pages) Integrated Circuit Systems – QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER

ICS853017
QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLKx /nPCLKx accepts LVPECL, CML, SSTL and other
differential signals. Both V and V must meet the V and
SWING
OH
PP
V input requirements. Figures 2A to 2E show interface
CMR
examples for the HiPerClockS PCLKx/nPCLKx input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3. 3V
PCLK
nPCLK _HiPerClockS
Input
R1
R2
84
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
3.3V
LVD S
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPC LK
H iPerC loc k S
PC L K / n PC L K
R1
R2
1K
1K
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V LVPECL
3.3V
Zo = 50 Ohm
R3
R4
84
84
C1
Zo = 50 Ohm
C2
R5
R6
100 - 200 100 - 200
R1
R2
125 125
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
IDT^™ / ICS^™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
8
ICS853017AM REV. B OCTOBER 24, 2007