ICS853017 Datasheet, PDF (11/15 Pages) Integrated Circuit Systems – QUAD, 1-TO-1 DIFFERENTIAL-TO-2.5V/3.3V/5V LVPECL/ECL RECEIVER

ICS853017
QUAD, 1-TO-1, DIFFERENTIAL-TO-2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
POWER CONSIDERATIONS
PRELIMINARY
This section provides information on power dissipation and junction temperature for the ICS853017.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853017 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 5.5V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * I = 5.5V * 46mA = 253mW
MAX
CC_MAX
EE_MAX
• Power (outputs) = 30.94mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 * 30.94mW = 123.76mW
Total Power (5.5V, with all outputs switching) = 123.76mW + 253mW = 376.76mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ * Pd_total + T
JA
A
Tj = Junction Temperature
θ = Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 46.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.377W * 46.2°C/W = 102.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 20-PIN SOIC, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
Single-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
65.7°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
46.2°C/W
39.7°C/W
500
57.5°C/W
36.8°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT^™ / ICS^™ 2.5V, 3.3V, 5V LVPECL/ECL RECEIVER
11
ICS853017AM REV. B OCTOBER 24, 2007