9DBV0541 Datasheet, PDF (8/16 Pages) Integrated Circuit Systems – HCSL compatible differential input

9DBV0541 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = T_COM or T_IND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Duty Cycle Distortion
t_DCD
Measured differentially, @100MHz
-1
-0.1
1
%
1,3
Skew, Input to Output
t_pdBYP
Bypass Mode, V_T = 50%
1800
2342
3000
ps
1
Skew, Output to Output
t_sk3
V_T = 50%
37
50
ps
1,4
Jitter, Cycle to cycle
t_{jcy c-cy c}
Additive Jitter in Bypass Mode
0.1
5
ps
1,2
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
4 _{All outputs at default slew rate}
Electrical Characteristics–Phase Jitter Parameters
TA = T_COM or T_IND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Additive Phase Jitter,
Bypass Mode
SYMBOL
CONDITIONS
MIN
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
t_{jphSGMIIM0 rollover < 1.5MHz, -40db/decade rolloff > 10MHz}
TYP
0.1
0.1
0.01
0.00
165
MAX
5
0.4
0.4
0.1
200
INDUSTRY
LIMIT UNITS Notes
N/A ps (p-p) 1,2,3,5
N/A
ps
(rms)
1,2,3,4,5
N/A
ps _1,2,3,4
(rms)
N/A
ps _1,2,3,4
(rms)
fs
N/A
(rms) ^1,6
t_jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251
300
N/A
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]}
5 _{Driven by 9FGV0831 or equivalent}
6 _{Driven by Rohde&Schwarz SMA100}
fs
1,6
(rms)
5 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
8
REVISION B 08/28/14