8T33FS6111 Datasheet, PDF (8/28 Pages) Integrated Device Technology – Fully differential architecture from input to all outputs

8T33FS6111 DATA SHEET
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V₁= V_CC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V₁in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and V_CC = 3.3V, R1 and R2
value should be adjusted to set V₁ at 1.25V. The values below are for
when both the single ended swing and V_CC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V_IL cannot be less
than -0.3V and V_IH cannot be more than V_CC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLKx/nCLKx Inputs
For applications not requiring the use of a differential input, both the
CLKx and nCLKx pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from CLKx to
ground. For applications
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL LVPECL/HSTL
8
FANOUT BUFFER
REVISION 1 12/02/14