8T33FS6111 Datasheet, PDF (1/28 Pages) Integrated Device Technology – Fully differential architecture from input to all outputs

Low Voltage 2.5V/3.3V Differential
LVPECL/HSTL Fanout Buffer
8T33FS6111
DATA SHEET
General Description
The 8T33FS6111 is a bipolar monolithic differential clock fanout
buffer. Designed for most demanding clock distribution systems, the
8T33FS6111 supports various applications that require distribution
of precisely aligned differential clock signals. Using SiGe:C
technology and a fully differential architecture, the device offers very
low skew outputs and superior digital signal characteristics. Target
applications for this clock driver is high performance clock distribution
in computing, networking and telecommunication systems.
The 8T33FS6111 is designed for low skew clock distribution systems
and supports clock frequencies up to 2.7GHz. The device accepts
two clock sources. The CLKA input can be driven by LVPECL
compatible signals, the CLKB input accepts HSTL or LVPECL
compatible signals. The selected input signal is distributed to 10
identical, LVPECL outputs. If V_BB is connected to the CLKA input and
bypassed to GND by a 10nF capacitor, the 8T33FS6111 can be
driven by single-ended LVPECL signals utilizing the V_BB bias voltage
output.
In order to meet the tight skew specification of the device, both
outputs of a differential output pair should be terminated, even if only
one output is used. In the case where not all ten outputs are used,
the output pairs on the same package side as the parts being used
on that side should be terminated.
The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply.
Pin Assignment
V_CC
CLK_SEL
32 31 30 29 28 27 26 25
1
24
2
23
Q3
nQ3
CLKA ³
22 _Q4
nCLKA ⁴
V_BB ⁵
8T33FS6111
21 _nQ4
20 _Q5
CLKB ⁶
19 _nQ5
nCLKB 7
18 _Q6
V_EE 8
17 _nQ6
9 10 11 12 13 14 15 16
Features
• 1:10 differential clock distribution
• 28ps typical output skew
• Fully differential architecture from input to all outputs
• SiGe:C technology supports near-zero output skew
• Supports DC to 2.7GHz operation of clock or data signals
• LVPECL compatible differential clock outputs
• LVPECL/HSTL compatible differential clock inputs
• Single 3.3V or 2.5V supply
• Standard 32-Lead VFQFN package
• Standard 32-lead LQFP package
• Standard 32-lead TQFP package with EPAD
• -40°C to 85°C ambient operating temperature
Block Diagram
V_CC
CLKA
nCLKA
0
1
V_CC
CLKB
nCLKB
CLK_SEL
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
V_BB
.
8T33FS6111 REVISION 1 12/02/14
1
©2014 Integrated Device Technology, Inc.