89HPES24NT3 Datasheet, PDF (8/31 Pages) Integrated Device Technology – 24-Lane 3-Port Non-Transparent PCI Express® Switch

IDT 89HPES24NT3 Data Sheet
Pin Characteristics
Note: Some input pads of the PES24NT3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Inter-
face
SMBus
General Purpose I/O
System Pins
Pin Name Type Buffer I/O Type
PEALREV
PEARN[7:0]
I
LVTTL
Input
I
CML
Serial link
PEARP[7:0]
I
PEATN[7:0]
O
PEATP[7:0]
O
PEBLREV
PEBRN[7:0]
PEBRP[7:0]
I
LVTTL
Input
I
CML
Serial link
I
PEBTN[7:0]
PEBTP[7:0]
PECLREV
O
O
I
LVTTL
Input
PECRN[7:0]
PECRP[7:0]
PECTN[7:0]
I
CML
Serial link
I
O
PECTP[7:0]
PEREFCLKN[1:0]
PEREFCLKP[1:0]
O
I
LVPECL/ Diff. Clock
I
CML
Input
REFCLKM
I
LVTTL
Input
MSMBADDR[4:1]
I
LVTTL
Input
MSMBCLK
I/O
STI
MSMBDAT
I/O
SSMBADDR[5,3:1] I
Input
SSMBCLK
I/O
STI
SSMBDAT
GPIO[7:0]
I/O
I/O
LVTTL
Input,
High Drive
CCLKDS
CCLKUS
MSMBSMODE
I
LVTTL
Input
I
I
PENTBRSTN
I
PERSTN
I
RSTHALT
I
SWMODE[3:0]
I
Table 7 Pin Characteristics (Part 1 of 2)
Internal
Resistor
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
pull-up
pull-up
pull-up
pull-down
pull-down
pull-up
Notes
Refer to
Table 8
8 of 31
April 11, 2007