89HPES24NT3 Datasheet, PDF (1/31 Pages) Integrated Device Technology – 24-Lane 3-Port Non-Transparent PCI Express® Switch

24-Lane 3-Port Non-Transparent
PCI Express® Switch
®
89HPES24NT3
Data Sheet
Preliminary Information*
Device Overview
The 89HPES24NT3 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions offering the next-generation I/O inter-
connect standard. The PES24NT3 is a 24-lane, 3-port peripheral chip
that performs PCI Express Base switching with a feature set optimized
for high performance applications such as servers, storage, and commu-
nications/networking. It provides high-performance switching functions
between a PCIe® upstream port, a transparent downstream port, and a
non-transparent downstream port.
With non-transparent bridging (NTB) functionality, the PES24NT3
can be used standalone or as a chipset with IDT PCIe System Intercon-
nect Switches in multi-host and intelligent I/O applications such as
communications, storage, and blade servers where inter-domain
communication is required.
Features
◆ _{High Performance PCI Express Switch}
– Twenty-four PCI Express lanes (2.5Gbps), three switch ports
– Delivers 96 Gbps (12 GBps) of aggregate switching capacity
– Low latency cut-through switch architecture
– Support for Max Payload size up to 2048 bytes
– Supports one virtual channel and eight traffic classes
– PCI Express Base specification Revision 1.0a compliant
◆ _{Flexible Architecture with Numerous Configuration Options}
– Port arbitration schemes utilizing round robin
– Supports automatic per port link width negotiation (x8, x4, x2,
or x1)
– Static lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
◆ _{Non-Transparent Port}
– Crosslink support on NTB port
– Four mapping windows supported
• Each may be configured as a 32-bit memory or I/O window
• May be paired to form a 64-bit memory window
– Interprocessor communication
• Thirty-two inbound and outbound doorbells
• Four inbound and outbound message registers
• Two shared scratchpad registers
– Allows up to sixteen masters to communicate through the non-
transparent port
– No limit on the number of supported outstanding transactions
through the non-transparent bridge
– Completely symmetric non-transparent bridge operation
allows similar/same configuration software to be run
– Supports direct connection to a transparent or non-transparent
port of another switch
Block Diagram
Frame Buffer
3-Port Switch Core
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
Transaction Layer
Data Link Layer
Non-
Transparent
Bridge
Multiplexer / Demultiplexer
Phy
Phy
Phy
Logical Logical
Logical
Layer Layer
...
Layer
SerDes SerDes
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 31
*Notice: The information in this document is subject to change without notice
April 11, 2007
DSC 6925