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879893 Datasheet, PDF (8/16 Pages) Integrated Device Technology – Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator
879893 Datasheet
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
fOUT
fREF
BW
Output Frequency
Input Frequency
PLL Closed Loop Bandwidth
t(Ø)
tsk(o)
Propagation Delay, (Static Phase
Offset, CLKx to FB); NOTE 1, 2, 3
Output Skew;
NOTE 1, 2, 3, 4
within bank
bank-to-bank
any output to QFB
VDD = 3.3V±5%; FSEL = 111x
VDD = 3.3V±5%
fREF = 62.5MHz, FSEL = 1000
t
Rate of Period Change; NOTE 2
FSEL = XXX0
tjit(cc)
tCYCLE
tjit(per)
tjit(Ø)
tR / tF
tPZL, tPZH
tPLZ, tPHZ
tL
odc
Cycle-to-Cycle Jitter; NOTE 2, 3
Output Clock Period Deviation when
switching from primary input to
secondary; NOTE 2
Period Jitter; NOTE 2, 3
I/O Phase Jitter, (1); NOTE 2, 3
Output Rise/Fall Time
Output Enable Time; NOTE 2
Output Disable Time; NOTE 2
PLL Lock Time; NOTE 2
Output Duty Cycle
FSEL = XXX1
FSEL3 = 0
FSEL3 = 1
fREF = 62.5MHz, FSEL = 1000
FSEL3 = 0
FSEL3 = 1, measured on QBx
FB = 4;
FSEL [0:2] = 100 or 111 (1)
FB = 6;
FSEL [0:2] = 010 (1)
FB = 8; FSEL [0:2] = 001, 011
or 110 (1)
FB = 16;
FSEL [0:2] = 000 or 101 (1)
20% to 80%
Minimum
7.5
15
-55
-55
-600
-800
250
45
Typical
0.8 to 4
50
Maximum
200
100
120
130
50
135
280
175
260
350
180
245
700
850
150
150
30
40
25
30
600
10
10
10
55
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps/
cycle
ps/
cycle
ps/
cycle
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ms
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 2: These parameters are guaranteed by characterization. Not tested in production.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
©2017 Integrated Device Technology, Inc.
8
Revision B, January 10, 2017