82V3001 Datasheet, PDF (8/27 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
INDUSTRIAL TEMPERATURE RANGE
Table - 1 Pin Description (Continued)
Name
Type
Pin
Number
Description
C16o
(CMOS) O
24
Clock 16.384 MHz.
This output is a 16.384 MHz clock used for ST-BUS operation.
C8o
(CMOS) O
23
Clock 8.192 MHz.
This output is an 8.192 MHz clock used for ST-BUS operation.
C4o
(CMOS) O
20
Clock 4.096 MHz.
This output is a 4.096 MHz clock used for ST-BUS operation.
C2o
(CMOS) O
17
Clock 2.048 MHz.
This output is a 2.048 MHz clock used for ST-BUS operation.
C3o
(CMOS) O
16
Clock 3.088 MHz.
This output is a 3.088 MHz clock used for T1 applications.
C1.5o (CMOS) O 15 ^{Clock 1.544 MHz.}
This output is a 1.544 MHz clock used for T1 applications.
C6o
(CMOS) O
14
Clock 6.312 MHz.
This output is a 6.312 MHz clock used for DS2 applications.
Frame Pulse ST-BUS 8.192 Mb/s.
F32o (CMOS) O 40 This is an 8 kHz 31 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
Frame Pulse ST-BUS 8.192 Mb/s.
F16o (CMOS) O 39 This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
F8o
(CMOS) O
36
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
Frame Pulse ST-BUS 2.048 Mb/s.
F0o
(CMOS) O 33 This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
Receive Sync Pulse.
RSP (CMOS) O 41 This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
Transmit Sync Pulse.
TSP (CMOS) O 42 This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
Test Serial Data Out.
TDO (CMOS) O 29 JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state if JTAG scan is
not enabled.
TDI
I
32
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V_DD.
Test Reset.
TRST
I
30 Asynchronously initializes the JTAG TAP controller by putting it in Test-Logic-Reset state. This pin is internally pulled up
to V_DD. It is connected to the ground for normal applications.
TCK
I
28
Test Clock.
Provides a clock to JTAG test logic.
TMS
I
31
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V_DD.
IC0, IC1, IC2
-
53, 54, 55
Internal Connection.
Internal Use. These pins should be connected to V_SS when in normal operation.
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