82V3001 Datasheet, PDF (17/27 Pages) Integrated Device Technology – WAN PLL WITH SINGLE REFERENCE INPUT

IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
In the case of the IDT82V3001A, the output signal phase continuity is
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns/125 µs. This meets AT&T TR62411 maximum
phase slope requirement of 7.6 ns/125 µs and Telcordia GR-1244-
CORE (81 ns/1.326 ms).
4.12 PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many
factors, which include:
i) Initial input to output phase difference
ii) Initial input to output frequency difference
iii) Synchronizer loop filter
iv) Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3001A
loop filter and limiter were optimized to meet AT&T TR62411 jitter
transfer and phase slope requirements. Consequently, phase lock time,
which is not a standards requirement, may be longer than in other
applications. See Table - 7 for Maximum Phase Lock Time.
The IDT82V3001A provides a fast lock pin (FLOCK), which enables
the DPLL to lock to an incoming reference within approximately 500 ms
when set high.
INDUSTRIAL TEMPERATURE RANGE
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