82P33831 Datasheet, PDF (8/13 Pages) Integrated Device Technology – Composite clock inputs

82P33831 SHORT FORM DATA SHEET
Table 1: Pin Description (Continued)
Pin No.
C9, A9, D8
A12
B12
A10
B10
E9
G9
H9
J9
B11
C11
D9
E5
D10
C5
F1
K3
Name
CAP1, CAP2,
CAP3
XTAL1_IN
XTAL1_OUT
XTAL2_IN
XTAL2_OUT
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
INT_REQ
MPU_MODE1/
I2CM_SCL
MPU_MODE0/
I2CM_SDA
I2C_AD2
I2C_AD1
I2C_SCL
I2C_SDA
TMS
TRSTB
I/O
I
O
I
O
O
O
O
O
Tri-state
I/O
pull-down
I
pull-down
I
pull-down
I
I/O
I
pull-up
I
pull-down
Type
Description
Miscellaneous
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors
are be part of the power filtering.
Analog
Analog
Analog
Analog
Crystal oscillator 1 input.
Determines first of two frequency families (Sonet/SDH, Ethernet or Ethernet*66/64) available
for APLL3. Connect to ground if XTAL1 is not used.
Crystal oscillator 1 output.
Leave open if XTAL1 is not used.
Crystal oscillator 2 input.
Determines first of two frequency families (chosen from Sonet/SDH, Ethernet or Ethernet*66/
64) available for APLL3. Connect to ground if XTAL2 is not used
Crystal oscillator 2 output.
Leave open if XTAL2 is not used.
Lock Signal
CMOS
CMOS
CMOS
DPLL3_LOCK
This pin goes high when DPLL3 is locked
DPLL2_LOCK
This pin goes high when DPLL2 is locked
DPLL1_LOCK
This pin goes high when DPLL1 is locked
Microprocessor Interface
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
CMOS/ ^{01 ~ 10: Reserved}
Open Drain ^{11: I2C master (EEPROM) mode}
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
CMOS
I2C_AD2: Device Address Bit 2
I2C_AD[2:1] pins are the address bus of the microprocessor interface.
CMOS
I2C_AD1: Device Address Bit 1
I2C_AD[2:1] pins are the address bus of the microprocessor interface.
CMOS
I2C_SCL: Serial Clock Line
The serial clock is input on this pin.
Open Drain
I2C_SDA: Serial Data Input/Output
This pin is used as the input/output for the serial data.
JTAG (per IEEE 1149.1)
CMOS
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND
8
10G/40G SYNCHRONOUS ETHERNET
REVISION 2 12/08/14