82P33831 Datasheet, PDF (5/13 Pages) Integrated Device Technology – Composite clock inputs

82P33831 SHORT FORM DATA SHEET
1
PIN ASSIGNMENT
1
2
3
4
5
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7
8
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10
11
12
A OUT5_POS OUT5_NEG OUT6_POS OUT6_NEG VDDAO OUT12_POS VDDAO OUT11_POS CAP2
XTAL2_IN
SONET/SDH/LO
S3
XTAL1_IN
A
B
VSSAO
VDDAO
VDDAO
VSSAO
VSSAO OUT12_NEG VSSAO OUT11_NEG
VSSA
XTAL2_OUT ^MPU_MODE1/I XTAL1_OUT
2CM_SCL
B
C
VDDA
VSSA
VSS
OUT7
I2C_SDA
VDDA
VDDA
IC
CAP1
IC
MPU_MODE0/I MFRSYNC_2
2CM_SDA
K_1PPS
C
D
VSSA
VDDA
VSSCOM
VSSD
VDDD
VSSA
VSSA
CAP3
I2C_AD2 I2C_SCL
OUT10
OUT9
D
E
OSCI
VSSA
IC
VDDDO
I2C_AD1
VDDD0
VSSDO
VSSA DPLL3_LOCK IN14
IN13
FRSYNC_8K_
1PPS
E
F
TMS
VDDA
VSSA
VSSDO
VSS
VSSD
VDDD
VSSA
VDDA
IN12
IN8_NEG
IN8_POS
F
G
TCK
VDDA
IC
VSS
VSS
VSS
IC
VSS DPLL2_LOCK IN11
IN7_NEG
IN7_POS
G
H
XO_FREQ0/
LOS0
VDDA
VSSA
VSS
VSS
VSS
VSS
VSS DPLL1_LOCK IN10
VSSD
VDDD_1_8 _H
J
XO_FREQ1/ XO_FREQ2/
LOS1
LOS2
VSS
VSS
VSS
VSS
VSS
VSS
INT_REQ
IN9
IN6_NEG
IN6_POS
J
K
VDDA
VDDA
TRSTB
VSSAO
OUT2
RSTB
VSSDO
MS_SL
IN2
IN1
IN5_NEG
IN5_POS
K
L
VSSA
VSSA
TDI
VDDAO
TDO
IC
VDDDO
OUT1
VSSD
VDDD_1_8 IN4_NEG
IN4_POS
L
M ^{OUT4_POS OUT4_NEG VSSAO}
VDDAO OUT3_POS OUT3_NEG VSSDO
VDDDO OUT8_POS OUT8_NEG IN3_NEG
IN3_POS _M
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Figure 1. Pin Assignment (Top View)
REVISION 2 12/08/14
5
SYNCHRONIZATION MANAGEMENT UNIT FOR IEEE 1588 AND
10G/40G SYNCHRONOUS ETHERNET