82P33814_17 Datasheet, PDF (8/12 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet

82P33814 Datasheet
Table 1: Pin Description (Continued)
Pin No.
40, 62
42, 53
19,23
73 (e_PAD)
Name
VDDD
VDDD_1_8
VSSAO
VSS
I/O
Power
Power
Ground
Ground
Type
Description
VDDD: Digital Core Power - +3.3V DC nominal
VDDD_1_8: Digital Core Power - +1.8V DC nominal
VSSAO: Ground
-
VSS: Ground
2.1 RECOMMENDATIONS FOR UNUSED INPUT
AND OUTPUT PINS
2.1.1
INPUTS
Control Pins
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
Single-Ended Clock Inputs
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Inputs
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
2.1.2
OUTPUTS
Status Pins
For applications not requiring the use of a status pin, we recommend
bringing out to a test point for debugging purposes.
Single-Ended Clock Outputs
All unused single-ended clock outputs can be left floating, or can be
brought out to a test point for debugging purposes.
Differential Clock Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output pair
©2017 Integrated Device Technology, Inc.
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Revision 7, January 9, 2017