7005S35JI Datasheet, PDF (8/21 Pages) Integrated Device Technology – HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Waveform of Read Cycles⁽⁵⁾
tRC
ADDR
CE
tAA⁽⁴⁾
tACE⁽⁴⁾
tAOE⁽⁴⁾
OE
Military, Industrial and Commercial Temperature Ranges
R/W
DATAOUT
BUSYOUT
tLZ⁽¹⁾
VALID DATA⁽⁴⁾
tBDD^(3,4)
tOH
tHZ⁽²⁾
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NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
Timing of Power-Up Power-Down
CE
tPU
ICC
ISB
tPD
,
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6.842