7005S35JI Datasheet, PDF (13/21 Pages) Integrated Device Technology – HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read with BUSY^(2,5)
(M/S = VIH)⁽⁴⁾
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
tAPS⁽¹⁾
VALID
ADDR"B"
BUSY"B"
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD⁽³⁾
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
VALID
2738 drw 13
Timing Waveform of Write with BUSY
tWP
R/W"A"
BUSY"B"
tWB⁽³⁾
R/W"B"
(2)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version..
(1)
tWH
2738 drw 14
61.432