DAC1653Q Datasheet, PDF (78/101 Pages) Integrated Device Technology – Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50

Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
Table 31. Sync_request control …continued
SEL_SYNC[2:0] Description
100
sync_request active when state machine of lane 2 is in CS_INIT mode
101
sync_request active when state machine of lane 3 is in CS_INIT mode
110
sync_request fixed to 1
111
sync_request fixed to 0
11.7.5.7 Inter-lane alignment
This module handles the alignment of the logical lanes based on the ILA sequence
described in the JESD204B specification. Inter-lane alignment starts when all lanes are
locked and at reception of the first non-K28.5 (or /K/) symbol.
During the ILA sequence, the K28.3 (/A/ symbol) is used to align the data streams. During
this sequence, the length (K) of the multi-frame is measured. This value is used by the
lane monitoring and correction process. The value is also used for the MDS circuitry,
where the SYSREF signal is expected to be a multiplication of the multi-frame length (K)
in the JESD204B specification.
During the second multi-frame, the JESD204B configuration data of each physical lane is
stored in register blocks x0120 and x0140 (see Figure 53). The DAC165xQ does not do
anything with these configuration data. They are only made available for the host
controller.
BLOCK nnn0h: JESD204 READ CONFIGURATION (DAC X/Y)
JESD204 CONFIGURATION
CONFIG 0 P_LN_DID
CONFIG 1 P_LN_ADJ_CNT
CONFIG 2 P_LN_ADJ_DIR
P_LN_ADJ_PH
CONFIG 3 P_LN_SCR
CONFIG 4 P_LN_F
CONFIG 5
CONFIG 6 P_LN_M
CONFIG 7 P_LN_CS
CONFIG 8 P_LN_SBCLSS_VS
CONFIG 9 P_LN_JESD_VS
CONFIG 10 P_LN_HD
CONFIG 11 P_LN_RES1
CONFIG 12 P_LN_RES2
CONFIG 13 P_LN_FCHK
P_LN_BID
P_LN_LID
P_LN_L
P_LN_K
P_LN_N
P_LN_N’
P_LN_S
P_LN_CF
Fig 53. JESD204 read configuration for physical lanes overview
DAC1653Q/DAC1658Q
Advance data sheet
Rev. 1.03 — 13 May 2013
© IDT 2013. All rights reserved.
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