DAC1653Q Datasheet, PDF (74/101 Pages) Integrated Device Technology – Quad 16-bit DAC: 10 Gbps JESD204B interface: up to 1.50

Integrated Device Technology
DAC1653Q/DAC1658Q
Quad 16-bit DAC: 10 Gbps JESD204B interface; up to 1.50 Gsps
11.7.5.3 Scrambling
The descrambler is a 16-bit parallel self-synchronous descrambler based on the
polynomial 1 + x¹⁴ + x¹⁵. From the JESD204B specification, the scrambling/descrambling
process only occurs on the user data, not on the code group synchronization or the ILA
sequence. After two received bytes, the descrambler is correctly set up to decode the data
in the proper way. However, it the initial state of the descrambler bits is set incorrectly, the
two first decoded bytes are decoded incorrectly. The JESD204B specification proposes
an initial state for both scrambler and descrambler to avoid this.
Using registers INIT_DESCR_P_LNx_XY any kind of intitial state can be set in the
DAC165xQ. The descrambling process starts when the ILA sequence has finished. This
process can be turned off by deasserting bit DESCR_EN_XY in register ILA_CTRL_1_XY
.
11.7.5.4 Lane swapping and selection
If the physical lanes do not match with the ordering of the transmitter lanes, they can be
reordered using the lane swapping module. As the DAC165xQ allows various LMF
configurations , it is important that the lane swapping respects the following reordering
constraints linked to the L value (see Table 28).
Table 28. Logical lanes versus L values
L value
Logical lanes used for the Sample assembly module
Binary Decimal
DAC A/B
100
4
logical lane 0
logical lane 1
logical lane 2
logical lane 3
010
2
logical lane 0
logical lane 2
001
1
DAC C/D
logical lane 0
100
4
logical lane 0
logical lane 1
logical lane 2
logical lane 3
010
2
logical lane 0
logical lane 2
001
1
logical lane 0
The selection of the logical lanes can be is specified by the LN_SEL_L_LNx_XY bits of
register LN_SEL_XY .
Table 29 shows the possible choices regarding the value of the L parameter.
DAC1653Q/DAC1658Q
Advance data sheet
Rev. 1.03 — 13 May 2013
© IDT 2013. All rights reserved.
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