IDT82V3385_10 Datasheet, PDF (77/145 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL

IDT82V3385
SYNCHRONOUS ETHERNET WAN PLL
IN2_CNFG - Input Clock 2 Configuration
Address: 17H
Type: Read / Write
Default Value: 00000000
7
6
5
4
DIRECT_DIV
LOCK_8K
BUCKET_SEL1 BUCKET_SEL0
3
IN_FREQ3
2
IN_FREQ2
1
IN_FREQ1
0
IN_FREQ0
Bit
Name
Description
7
DIRECT_DIV Refer to the description of the LOCK_8K bit (b6, 17H).
This bit, together with the DIRECT_DIV bit (b7, 17H), determines whether the DivN Divider or the Lock 8k Divider is used for
IN2:
6
LOCK_8K
DIRECT_DIV bit
0
0
1
1
LOCK_8K bit
0
1
0
1
Used Divider
Both bypassed (default)
Lock 8k Divider
DivN Divider
Reserved
These bits select one of the four groups of leaky bucket configuration registers for IN2:
00: Group 0; the addresses of the configuration registers are 31H ~ 34H. (default)
5-4
BUCKET_SEL[1:0] 01: Group 1; the addresses of the configuration registers are 35H ~ 38H.
10: Group 2; the addresses of the configuration registers are 39H ~ 3CH.
11: Group 3; the addresses of the configuration registers are 3DH ~ 40H.
These bits set the DPLL required frequency for IN2
0000: 8 kHz. (default)
0001: 1.544 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘1’) / 2.048 MHz (when the IN_SONET_SDH bit (b2, 09H) is ‘0’).
0010: 6.48 MHz.
0011: 19.44 MHz.
3-0
IN_FREQ[3:0]
0100: 25.92 MHz.
0101: 38.88 MHz.
0110 ~ 1000: Reserved.
1001: 2 kHz.
1010: 4 kHz.
1011 ~ 1111: Reserved.
For the IN2, the required frequency should not be set higher than frequency of the input clock.
Programming Information
77
May 14, 2010