English
Language : 

IDT82V3385_10 Datasheet, PDF (24/145 Pages) Integrated Device Technology – SYNCHRONOUS ETHERNET WAN PLL
IDT82V3385
SYNCHRONOUS ETHERNET WAN PLL
3.6.2
FORCED SELECTION
In Forced selection, the selected input clock is set by the
T0_INPUT_SEL[3:0] / T4_INPUT_SEL[3:0] bits. The results of input
clocks quality monitoring (refer to Chapter 3.5 Input Clock Quality Moni-
toring) do not affect the input clock selection.
3.6.3
AUTOMATIC SELECTION
In Automatic selection, the input clock selection is determined by its
validity, priority and locking allowance configuration. The validity
depends on the results of input clock quality monitoring (refer to
Chapter 3.5 Input Clock Quality Monitoring). Locking allowance is con-
figured by the corresponding INn_VALID bit(1  n  5). Refer to
Figure 6. In all the qualified input clocks, the one with the highest priority
is selected. The priority is set by the corresponding
INn_SEL_PRIORITY[3:0] bits (1  n  5). If more than one qualified
input clock INn is available and has the same priority, the input clock
with the smallest ‘n’ is selected.
Validity
Priority
Locking Allowance
No
No
No
Input Clock Quality Monitoring
(Activity, Frequency)
INn = '1', (1  n 5)
INn_SEL_PRIORITY[3:0]
'0000', ((1  n  5))
INn_VALID = '0',
((1  n  5))
Yes
Yes
Yes
All qualified input clocks are available for Automatic selection
Figure 6. Qualified Input Clocks for Automatic Selection
Table 9: Related Bit / Register in Chapter 3.6
Bit
Register
EXT_SW
T0_INPUT_SEL[3:0]
T4_LOCK_T0
T0_FOR_T4
T4_INPUT_SEL[3:0]
INn_SEL_PRIORITY[3:0] (1  n  5)
INn_VALID (1  n  5)
INn (1  n  5)
T4_T0_SEL
MON_SW_PBO_CNFG
T0_INPUT_SEL_CNFG
T4_INPUT_SEL_CNFG
IN1_IN2_SEL_PRIORITY_CNFG
IN3_IN4_SEL_PRIORITY_CNFG
IN5_SEL_PRIORITY_CNFG
REMOTE_INPUT_VALID1_CNFG,
REMOTE_INPUT_VALID2_CNFG
INPUT_VALID1_STS, INPUT_VALID2_STS
T4_T0_REG_SEL_CNFG
Note: * The setting in the 26 ~ 2C registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
Address (Hex)
0B
50
51
27 ~ 28, 2B
4C, 4D
4A, 4B
07
Functional Description
24
May 14, 2010