IDT70V5388 Datasheet, PDF (7/29 Pages) Integrated Device Technology – 3.3V 64/32K X 18 SYNCHRONOUS FOURPORT STATIC RAM

IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control^(1,2,3)
Upper Byte Lower Byte
OE
CLK CE0
CE1
UB
LB
R/W
I/O9-17
I/O0-8
MODE
X
↑
H
X
X
X
X
High-Z
High-Z Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z All Bytes Deselected
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
DIN
High-Z Write to Upper Byte Only
X
↑
L
H
L
L
L
DIN
DIN
Write to Both Bytes
L
↑
L
H
H
L
H
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
H
H
DOUT
High-Z Read Upper Byte Only
L
↑
L
H
L
L
H
DOUT
DOUT
Read Both Bytes
H
↑
X
X
X
X
X
High-Z
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CNTLD, CNTINC, CNTRST = VIH.
3. OE is an asynchronous input signal.
5649 tbl 03
Truth Table II—Address Counter & Mask Control^(1,2)
Previous Internal
External Internal Address
Address Address Used CLK CNTLD CNTINC CNTRST MKLD
I/O
MODE
X
X
0
↑
X
X
L⁽³⁾
X
DI/O(0) Counter Reset to Address 0
An
Ap
Ap
↑
X
X
H
L
DI/O(p) Counter disabled (Ap reused)
An
X
An
↑
L⁽³⁾
X
H
H
DI/O (n) External Address Used
An
Ap
Ap
↑
H
H
H
H
DI/O(p) External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1⁽⁵⁾ ↑
H
L⁽⁴⁾
H
H
DI/O(p+1)⁽⁵⁾ Counter Enabled—Internal Address generation
5649 tbl 04
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, LB, UB and OE.
3. CNTLD and CNTRST are independent of all other memory control signals including CE0, CE1 and LB, UB.
4. The address counter advances if CNTINC = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, LB, UB.
5. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle).
6.472