IDT7035S_15 Datasheet, PDF (7/19 Pages) Integrated Device Technology – HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM

IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range⁽⁴⁾
7035X15
Com'l Only
7035X20
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
ns
tAA
Address Access Time
____
15
____
20
ns
tACE
Chip Enable Access Time⁽³⁾
____
15
____
20
ns
tABE
Byte Enable Access Time⁽³⁾
____
15
____
20
ns
tAOE
Output Enable Access Time
____
10
____
12
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time^(1,2)
3
____
3
____
ns
tHZ
Output High-Z Time^(1,2)
____
10
____
12
ns
tPU
Chip Enable to Power Up Time ⁽²⁾
tPD
Chip Disable to Power Down Time⁽²⁾
tSOP
Semaphore Flag Update Pulse (OE or SEM)⁽³⁾
0
____
0
____
ns
____
15
____
20
ns
10
____
10
____
ns
tSAA
Semaphore Address Access Time⁽³⁾
____
15
____
20
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
4088 tbl 12
Waveform of Read Cycles⁽⁵⁾
tRC
ADDR
tAA ⁽⁴⁾
CE
tACE ⁽⁴⁾
tAOE ⁽⁴⁾
OE
UB, LB
tABE ⁽⁴⁾
R/W
DATAOUT
tLZ ⁽¹⁾
tOH
(4)
VALID DATA
BUSYOUT
tHZ ⁽²⁾
NOTES:
tBDD ^(3,4)
4088 drw 05
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has
no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.742