IDT7035S_15 Datasheet, PDF (14/19 Pages) Integrated Device Technology – HIGH-SPEED 8K x 18 DUAL-PORT STATIC RAM

IDT7035S/L
High-Speed 8K x 18 Dual-Port Static RAM
Waveform of Interrupt Timing⁽¹⁾
tWC
ADDR"A"
tAS⁽³⁾
(2)
INTERRUPT SET ADDRESS
CE"A"
Industrial and Commercial Temperature Ranges
tWR ⁽⁴⁾
R/W"A"
INT"B"
ADDR"B"
CE"B"
tINS⁽³⁾
tAS ⁽³⁾
tRC
INTERRUPT CLEAR ADDRESS ⁽²⁾
4088 drw 15
OE"B"
INT"B"
tINR⁽³⁾
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
4088 drw 16
Truth Table III — Interrupt Flag^(1,2)
Left Port
R/WL
CEL
OEL
A0L-A12L
INTL
R/WR
CER
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L⁽³⁾
L
L
X
L
L
1FFE
H⁽²⁾
X
X
Right Port
OER
A0R-A12R
X
X
L
1FFF
X
1FFE
X
X
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
INTR
Function
L⁽²⁾ Set Right INTR Flag
H⁽³⁾ Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
4088 tbl 16
61.442