ICS9FG104D Datasheet, PDF (7/17 Pages) Integrated Device Technology – Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA

ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG104D
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC
(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC _(h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD _(h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X_(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address DC_(h)
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P
stoP bit
ACK
IDT^® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
Index Block Read Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address DC_(h)
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address DD_(h)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P
stoP bit
Byte N + X - 1
1541C—12/16/10