ICS9150-01 Datasheet, PDF (7/14 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

ICS9150- 01
Byte 5: Peripheral Clock Register
Byte 6: Optional Register for Future
BIT PIN# PWD
DES C RIP TIO N
Bit 7
-
1 Reserved
Bit 6
2
1 IOAPIC2 (Act/Inact)
Bit 5 54
1 IOAPIC1 (Act/Inact)
Bit 4 55
1 IOAPIC0 (Act/Inact)
Bit 3
-
1 Reserved
Bit 2
-
1 Reserved
Bit 1
-
1 Reserved
Bit 0
3
1 REF0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Power Management
Clock Enable Configuration
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
1
1
1
1
1
1
1
1
DES C RIP TIO N
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
CPU_STOP# PCI_STOP#
0
0
0
1
1
0
1
1
CPUCLK
Low
Low
66.6/60 MHz
66.6/60 MHz
PCICLK
Low
33.3/30 MHz
Low
33.3/30 MHz
Other Clocks,
SDRAM,
REF,
IOAPICs
Running
Running
Running
Running
Crystal
Running
Running
Running
Running
VCOs
Running
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock
pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing
and signal loading may have a large impact on the initial clock distortion also.
ICS9150-01 Power Management Requirements
SIGNAL
CPU_ STOP#
PCI_STOP#
SIGNAL STATE
0 (Disabled)²
1 (Enabled)¹
0 (Disabled)²
1 (Enabled)¹
Latency
No. of rising edges of free running
PCICLK
1
1
1
1
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
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