ICS9150-01 Datasheet, PDF (6/14 Pages) Integrated Circuit Systems – Pentium Pro™ and SDRAM Frequency Generator

ICS9150- 01
Select Functions
FUNCTION
DESCRIPTION
Tri - State
Test Mode
CPU
Hi-Z
TCLK/2¹
PCI,
PCI_F
Hi-Z
TCLK/4¹
Notes:
1. REF is a test clock on the X1 inputs during test mode.
OUTPUTS
SDRAM
Hi-Z
TCLK/2¹
REF
Hi-Z
TCLK¹
IOAPIC
Hi-Z
TCLK¹
Byte 1: CPU Clock Register
BIT PIN# PWD
DES C RIP TIO N
Bit 7 -
1 Reserved
Bit 6 -
1 Reserved
Bit 5 -
1 Reserved
Bit 4 46
1 CPUCLK4 (Act/Inact)
Bit 3 48
1 CPUCLK3 (Act/Inact)
Bit 2 49
1 CPUCLK2 (Act/Inact)
Bit 1 51
1 CPUCLK1 (Act/Inact)
Bit 0 52
1 CPUCLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 3: SDRAM Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
35
36
38
39
41
42
44
45
PWD
DES C RIP TIO N
1 SDRAM7 (Act/Inact)
1 SDRAM6 (Act/Inact)
1 SDRAM5 (Act/Inact)
1 SDRAM4 (Act/Inact)
1 SDRAM3 (Act/Inact)
1 SDRAM2 (Act/Inact)
1 SDRAM1 (Act/Inact)
1 SDRAM0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 2: PCICLK Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
8
16
14
13
12
11
9
PWD
1
1
1
1
1
1
1
1
DES C RIP TIO N
Reserved
PCICLK_F (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4: SDRAM Clock Register
BIT PIN# PWD
DES C RIP TIO N
Bit 7 24
1 SDRAM15 (Act/Inact)
Bit 6 25
1 SDRAM14 (Act/Inact)
Bit 5 32
Bit 4 33
1
SDRAM13 (Act/Inact)
Desktop Only
1
SDRAM12 (Act/Inact)
Desktop Only
Bit 3 18
1 SDRAM11 (Act/Inact)
Bit 2 19
1 SDRAM10 (Act/Inact)
Bit 1 21
1 SDRAM9 (Act/Inact)
Bit 0 22
1 SDRAM8 (Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
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