ICS8761I Datasheet, PDF (7/16 Pages) Integrated Device Technology – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

ICS8761I
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
TABLE 7A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDOX = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
f = 50MHz
-150
166.67
150
tsk(b) Bank Skew; NOTE 2, 6
50
tsk(o) Output Skew; NOTE 3, 6
250
f = 50MHz; NOTE 4, 7
70
tjit(cc) Cycle-to-Cycle Jitter; 6
f = 25MHz XTAL,
133.3MHz out
190
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7, 8
17
t
PLL Lock Time
1
L
t_R / t_F
Output Rise/Fall Time
20% to 80%
250
800
odc
Output Duty Cycle; NOTE 5, 7
45
55
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from V_DD/2 of the input to
V_DDOx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value.
Units
MHz
ps
ps
ps
ps
ps
ps
ms
ps
%
TABLE 7B. AC CHARACTERISTICS,
V_DD
=
V_DDA
=
3.3V±5%,
V
DDOX
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
f = 50MHz
-350
166.67
20
tsk(b) Bank Skew; NOTE 2, 6
50
tsk(o) Output Skew; NOTE 3, 6
250
f = 50MHz; NOTE 4, 7
70
tjit(cc) Cycle-to-Cycle Jitter; NOTE 6
f = 25MHz XTAL,
133.3MHz out
190
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7, 8
17
t_L
PLL Lock Time
1
t_R / t_F
Output Rise/Fall Time
20% to 80%
250
800
odc
Output Duty Cycle; NOTE 5, 7
45
55
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from V_DD/2 of the input to
V_DDOX/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value
Units
MHz
ps
ps
ps
ps
ps
ps
ms
ps
%
8761CYI
www.idt.com
REV. C JULY 27, 2010
7