ICS8761I Datasheet, PDF (11/16 Pages) Integrated Device Technology – LOW VOLTAGE, LOW SKEW, PCI / PCI-X CLOCK GENERATOR

ICS8761I
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8761I. In this
example, the input is driven by an 18pF parallel crystal. The
decoupling capacitors should be physically located near the
power pin. For ICS8761I, the unused clock outputs can be left
floating. The optional C1 and C2 are spare footprints for frequency
fine tuning.
VDD
R5 R6
U1
C1
SP
1K 1K
VDD
X1
25MHz,18pF
FB
C2
SP
VDD
C17
C16
0.1u
10u
1
2
REF_CLK
3
4
5
6
7
GND
XTAL1
XTAL2
VDD
XTAL_SEL
8 ^PLL_SEL
9
10
11
VDDA
VDD
D_SELC0
12
13
14
15
16
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
SP = Spare, Not Install
I_IC_CS_S8₈7₇6₆1₁I
VDDO
GND
48
47
FB_OUT
VDDOFB
FB_IN
VDD
FBDIV_SEL0
46
45
44
43
42
FBDIV_SEL1 ₄₁
MR
VDD
D_SELD0
40
39
38
D_SELD1
OED
OEB
D_SELB0
D_SELB1
37
36
35
34
33
GND
R1
36
Zo = 50
Zo = 50
R2
36
VDDO
VDD
Zo = 50
R3
36
Receiv er
Receiv er
Receiv er
Logic Input Pin Examples
Set Logic
Set Logic
VDD _{Input to '1'} VDD _{Input to '0'}
RU1
1K
To Logic
Input pins
RD1
SP
RU2
SP
To Logic
Input pins
RD2
1K
VDDO
(U1,5) (U1,9)
VDD
(U1,40)
(U1,44)
C6
C5
C4
C3
0.1u
0.1u
0.1u
0.1u
R4
36
VDD=3.3V
VDDO=3.3V
Zo = 50
Receiv er
(U1,19) (U1,23) (U1,27) (U1,31) (U1,50) (U1,54) (U1,58) (U1,62) (U1,46)
VDDO
C7
C8
C9
C10
C11
C12
C13
C14
C15
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
FIGURE 3. ICS8761I CLOCK GENERATOR SCHEMATIC EXAMPLE
8761CYI
www.idt.com
11
REV. C JULY 27, 2010