ICS844021I-01 Datasheet, PDF (7/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

ICS844021I-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
APPLICATION INFORMATION
PRELIMINARY
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844021I-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_DD and V_DDA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin.
To achieve optimum jitter performance, power supply isolation
is required. Figure 1 illustrates how a 10Ω resistor along with
a 10μF and a .01μF bypass capacitor should be connected to
each V pin.
DDA
3.3V or 2.5V
V_DD
.01μF 10Ω
V_DDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844021I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
33p
XTAL_IN
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
7
ICS844021BGI-01 REV. C SEPTEMBER 27, 2007