ICS83021I Datasheet, PDF (7/12 Pages) Integrated Circuit Systems – 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

ICS83021I
1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR
Parameter Measurement Information, continued
nCLK
CLK
Q0
V_DD
2
t
PD
Propagation Delay
V
DD
Q0
2
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V_DD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Single Ended Clock Input
V_REF
C1
0.1u
VDD
R1
1K
CLK
nCLK
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
7
ICS83031AMI REV. C OCTOBER 31, 2008