9FGU0441 Datasheet, PDF (7/15 Pages) Integrated Device Technology – Programmable Slew rate for each output

9FGU0441 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1.2 2.4 3.6 ^V/ns 1,2,3
0.8 1.7 2.5 ^V/ns 1,2,3
9
20
% _1,2,4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{600 750 850}
7
using oscilloscope math function. (Scope
mV
averaging on)
-150 26 150
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
763 1150
7
absolute value. (Scope averaging off)
-300 22
mV
7
Vswing
Vswing
Scope averaging off
300 1448
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 390 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
11 140 mV 1,6,7
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus amplitude settings.}
Electrical Characteristics–DIF Output Phase Jitter Parameters
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
t_jphPCIeG1
Phase Jitter, PLL Mode
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
27.7
1.0
1.9
0.4
MAX
40
1.3
2.2
0.6
IND.
LIMIT
86
3
3.1
1
UNITS Notes
ps (p-p) 1,2,3,5
ps _1,2,3,5
(rms)
ps _1,2,3,5
(rms)
ps
(rms)
1,2,3,5
t_jphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
0.4 0.6 0.7
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Calculated from Intel-supplied Clock Jitter Tool}
5 _{Applies to all differential outputs}
ps
(rms) ^1,2,3,5
REVISION A 09/24/14
7
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS