9FGU0441 Datasheet, PDF (3/15 Pages) Integrated Device Technology – Programmable Slew rate for each output

9FGU0441 DATASHEET
Pin Descriptions
Pin#
1
2
3
4
5
Pin Name
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
6 vSADR/REF1.5
7 GNDREF
8 GNDDIG
9 VDDDIG1.5
10 SCLK_3.3
11 SDATA_3.3
12 vOE0#
13 DIF0
14 DIF0#
15 GND
16 VDDO1.5
17 vOE1#
18 DIF1
19 DIF1#
20 GNDA
21 VDDA1.5
22 DIF2
23 DIF2#
24 vOE2#
25 VDDO1.5
26 GND
27 DIF3
28 DIF3#
29 vOE3#
30 GND
31 ^CKPWRGD_PD#
32 vSS_EN_tri
Type Pin Description
GND GND for XTAL
IN
Crystal input or Reference Clock input. Nominally 25MHz.
OUT Crystal output.
PWR Power supply for XTAL, nominal 1.5V
PWR VDD for REF output. nominal 1.5V.
LATCHED
I/O
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
GND Ground pin for the REF outputs.
GND Ground pin for digital circuitry
PWR 1.5V digital power (dirty power)
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin.
PWR Power supply for outputs, nominally 1.5V.
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
GND Ground pin for the PLL core.
PWR 1.5V power for the PLL core.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for outputs, nominally 1.5V.
GND Ground pin.
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
GND Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
LATCHED IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
REVISION A 09/24/14
3
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS