9DBV0231_16 Datasheet, PDF (7/17 Pages) Integrated Device Technology – 2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer

9DBV0231 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = T_AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
dV/dt
 dV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
1.9 3.2
4 V/ns 1,2,3
1.4 2.3 3.3 V/ns 1,2,3
5
20 % 1,2,4
Voltage High
Voltage Low
V_HIGH
V_LOW
Statistical measurement on single-ended signal _{660 779 850}
7
using oscilloscope math function. (Scope
mV
averaging on)
-150 21 150
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
835 1150 _mV
7
absolute value. (Scope averaging off)
-300 -42
7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 409 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14 140 mV 1,6
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 _{At default SMBus settings.}
Electrical Characteristics–Current Consumption
TA = T_AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
Operating Supply Current
I_DDA
I_DD
VDDA+VDDR, PLL Mode, @100MHz
VDD, All outputs active @100MHz
Powerdown Current
I_DDAPD
I_DDPD
VDDA+VDDR, PLL Mode, @100MHz
VDD, Outputs Low/Low
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input clock stopped.}
TYP
4.4
14.2
0.014
0.9
MAX
6
18
1
1.4
UNITS
mA
mA
mA
mA
NOTES
1
1
1, 2
1, 2
REVISION F 04/28/16
7
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER