9DB833 Datasheet, PDF (7/18 Pages) Integrated Circuit Systems – SMBus Interface; unused outputs can be disabled

9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
T_A = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Slew rate
Trf
Scope averaging on
Slew rate matching
∆Trf
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1
2
4 ^V/ns 1, 2, 3
20
% 1, 2, 4
Voltage High
Voltage Low
VHigh
Statistical measurement on single-ended signal _{660 800 850}
1
using oscilloscope math function. (Scope
mV
VLow
averaging on)
-150 14 150
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
806 1150 _mV
1
absolute value. (Scope averaging off)
-300 -1
1
Vswing
Vswing
Scope averaging off (Differential)
300 1552
mV 1, 2
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
∆-Vcross
Scope averaging off
Scope averaging off
250 375 550 mV 1, 5
18 140 mV 1, 6
1_{Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA.}
I_OH = 6 x I_REF and V_OH = 0.7V @ Z_O=50Ω (100Ω differential impedance).
2 _{Measured from differential waveform}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on}
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising}
edge (i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross}
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
PLL Bandwidth
PLL Jitter Peaking
Duty Cycle
BW
t_JPEAK
t_DC
-3dB point in High BW Mode (T_IND)
-3dB point in High BW Mode (T_COM)
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
1.5
2.7
4.1
MHz
1
2
2.7
4
MHz
1
0.7
1.1
1.4
MHz
1
1.5
2
dB
1
45
49
55
%
1
Duty Cycle Distortion
t_DCD Measured differentially, Bypass Mode @100MHz -2
2
%
1,4
Skew, Input to Output
t_pdBYP
Bypass Mode, V_T = 50% (T_IND)
Bypass Mode, V_T = 50% (T_COM)
t_pdPLL
PLL Mode V_T = 50%
Skew, Output to Output
t_sk3
V_T = 50%
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
1_{Guaranteed by design and characterization, not 100% tested in production.}
2500
4900
ps
1
2500
4500
ps
1,5
-250
-50
250
ps
1
50/60
ps
1,5
50
ps
1,3
50
ps
1,3
2 _{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
3 _{Measured from differential waveform}
4 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
5 _{First number is commercial temp, second number is industrial temp.}
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
7
9DB833
REV G 082515