9DB833 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – SMBus Interface; unused outputs can be disabled

9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Configuration
SRC_DIV# 1
VDDR 2
GND 3
SRC_IN 4
SRC_IN# 5
OE0# 6
OE3# 7
DIF_0 8
DIF_0# 9
GND 10
VDD 11
DIF_1 12
DIF_1# 13
OE1# 14
OE2# 15
DIF_2 16
DIF_2# 17
GND 18
VDD 19
DIF_3 20
DIF_3# 21
BYP#_HIBW_LOBW 22
SMBCLK 23
SMBDAT 24
48 VDDA
47 GNDA
46 IREF
45 LOCK
44 OE7#
43 OE4#
42 DIF_7
41 DIF_7#
40 PD#
39 VDD
38 DIF_6
37 DIF_6#
36 OE6#
35 OE5#
34 DIF_5
33 DIF_5#
32 GND
31 VDD
30 DIF_4
29 DIF_4#
28 SMB_ADR_tri
27 VDD
26 GND
25 GND
Notes:
Highlighted Pins are the differences between 9DB803 and 9DB833.
Pin 22 and Pin 28 are latched on power up. Please make sure that the
power supply to the pullup/pulldown resistors ramps at the same time
as the main supply to the chip.
Operating Mode Readback Table
BY P#_ LOB W_HI BW
Low
M id
Hig h
MODE
Bypass
PLL 100M Hi BW
PLL 100M Low BW
Byte0, bit 3
0
1
0
Byte 0 bit 1
0
0
1
Power Connections
Pin Number
VDD
GND
Description
2
3
SRC_IN/SRC_IN#
11,19,31,39 10,18, 25,32
DIF(7:0)
27
26
DIGITAL VDD/GND
48
47
Analog VDD/GND for PLL in IREF
For best results, treat pin 2 as analog VDD.
SMBus Address Selection and Readback
S MB_AD R_tri
Low
M id
Hig h
Address
DA/DB
D C/DD
D8 /D9
Tri-level Input Logic Levels
State of Pin
Low
M id
Hig h
Voltage
< 0.8 V
1 .2<V in <1.8 V
Vin > 2.0V
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
2
9DB833
REV G 082515