8101925 Datasheet, PDF (7/11 Pages) Integrated Device Technology – VCXO-to-LVCMOS/ LVTTL Output

8101925 Datasheet
Applications Information
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must be
taken with the package and load capacitance (C_L). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application Note.
The crystal’s load capacitance C_L characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (C_TUNE).
If the crystal’s C_L is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal’s C_L is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of C_L is dependent on the characteristics
of the VCXO. The recommended C_L in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
The frequency of oscillation in the third overtone mode is not
necessarily at exactly three times the fundamental frequency. The
mechanical properties of the quartz element dictate the position of
the overtones relative to the fundamental. The oscillator circuit may
excite both the fundamental and overtone modes simultaneously.
This will cause a nonlinearity in the tuning curve. This potential
problem is the reason VCXO crystals are required to be tested for
absence of any activity inside a ±200ppm window at three times the
fundamental frequency. Refer to F_{L_3OVT} and F_{L_3OVT_spurs} in the
Crystal Characteristics Table.
The crystal and external loop filter
components should be kept as
close as possible to the device.
Loop filter and crystal traces
should be kept short and
separated from each other. Other
signal traces should be kept
separate and not run underneath
the device, loop filter or crystal
components.
R_S
C_P C_S
C_TUNE
25MHz
C_TUNE
LF0
LF1
XTAL_IN
XTAL_OUT
VCXO Characteristics Table
Symbol Parameter
k_VCXO
C_{V_LOW}
C_{V_HIGH}
VCXO Gain
Low Varactor Capacitance
High Varactor Capacitance
Typical
15
9.8
22.7
Crystal Characteristics
Symbol
Parameter
Mode of Oscillation
f_N
Frequency
f_T
Frequency Tolerance
f_S
Frequency Stability
Operating Temperature Range
C_L
C_O
F_{L_3OVT}
F_{L_3OVT_spurs}
C_O / C₁
ESR
Load Capacitance
Shunt Capacitance
3^rd Overtone F_L
3^rd Overtone F_L Spurs
Pullability Ratio
Equivalent Series Resistance
Drive Level
Aging @ 25 ⁰C
Units
kHz/V
pF
pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth
Crystal
Frequency
(MHz)
R_S (k)
C_S (µF)
48Hz (Low)
25MHz
50
1
210Hz (Mid)
25MHz
220
0.03
478Hz (High)
25MHz
500
0.01
C_P (pF)
1500
270
100
Test Conditions
First Year
Ten Years
Minimum Typical Maximum
Fundamental
25
±20
±20
-40
+85
10
4
200
200
220
240
40
1
±3
±10
Units
MHz
ppm
ppm
0_C
pF
pF
ppm
ppm

mW
ppm
ppm
©2016 Integrated Device Technology, Inc.
7
Revision B, November 7, 2016