5T905 Datasheet, PDF (7/19 Pages) Integrated Device Technology – 2.5V Single Data Rate1:5 Clock Buffer Terabuffer

5T905 DATA SHEET
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS⁽¹⁾
Symbol
Parameter
Test Conditions⁽²⁾
Typ.
IDDQ
Quiescent VDD Power Supply Current
VDDQ = Max., Reference Clock = LOW⁽³⁾
20
Outputs enabled, All outputs unloaded
IDDQQ
Quiescent VDDQ Power Supply Current
VDDQ = Max., Reference Clock = LOW⁽³⁾
0.1
Outputs enabled, All outputs unloaded
IDDD
Dynamic VDD Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
10
Current per Output
IDDDQ
Dynamic VDDQ Power Supply
VDD = Max., VDDQ = Max., CL = 0pF
20
Current per Output
ITOT
Total Power VDD Supply Current
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
20
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF
25
ITOTQ
Total Power VDDQ Supply Current
VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF
20
VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF
40
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
Max
Unit
30
mA
0.3
mA
20
μA/MHz
30
μA/MHz
30
mA
40
40
mA
80
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol
Parameter
Value
Units
VDIF
Input Signal Swing⁽¹⁾
1
V
VX
Differential Input Signal Crossing Point⁽²⁾
900
mV
VTHI
Input Timing Measurement Reference Level⁽³⁾
Crossing Point
V
tR, tF
Input Signal Edge Rate⁽⁴⁾
1
V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC)
specification under actual use conditions.
2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVEPECL⁽¹⁾
Symbol
Parameter
Test Conditions
Min.
Typ.⁽²⁾
Max
Unit
Input Characteristics
IIH
Input HIGH Current⁽⁶⁾
VDD = 2.6V
VI = VDDQ/GND
—
—
±5
μA
IIL
Input LOW Current⁽⁶⁾
VDD = 2.6V
VI = GND/VDDQ
—
—
±5
VIK
Clamp Diode Voltage
VDD = 2.4V, IIN = -18mA
—
- 0.7
- 1.2
V
VIN
DC Input Voltage
- 0.3
—
3.6
V
VCM
DC Common Mode Input Voltage^(3,5)
915
1082
1248
mV
VREF
Single-Ended Reference Voltage^(4,5)
—
1082
—
mV
VIH
DC Input HIGH
1275
—
1620
mV
VIL
DC Input LOW
555
—
875
mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF.
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be refer-
enced.
6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
REVISION A 11/3/15
7
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™