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5T905 Datasheet, PDF (1/19 Pages) Integrated Device Technology – 2.5V Single Data Rate1:5 Clock Buffer Terabuffer | |||
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2.5V Single Data Rate1:5 Clock Buffer
Terabufferâ¢
5T905
DATA SHEET
FEATURES:
⢠Guaranteed Low Skew < 60ps (max)
⢠Very low duty cycle distortion
⢠High speed propagation delay < 2.5ns. (max)
⢠Up to 250MHz operation
⢠Very low CMOS power levels
⢠1.5V VDDQ for HSTL interface
⢠Hot insertable and over-voltage tolerant inputs
⢠3-level inputs for selectable interface
⢠Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input
interface
⢠Selectable differential or single-ended inputs and ï¬ve single-end-
ed outputs
⢠2.5V VDD
⢠Available in TSSOP package
⢠For new designs use functional replacement 8L30110
APPLICATIONS:
⢠Clock and signal distribution
DESCRIPTION:
The 5T905 2.5V single data rate (SDR) clock buffer is a user-selectable
single-ended or differential input to ï¬ve single-ended outputs buffer built on
advanced metal CMOS technology. The SDR clock buffer fanout from a
single or differential input to ï¬ve single-ended outputs reduces the loading
on the preceding driver and provides an efï¬cient clock distribution network.
The IDT5T905 can act as a translator from a differential HSTL, eHSTL,
1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to
HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled
by 3-level input signals that may be hard-wired to appropriate high-mid-low
levels. Multiple power and grounds reduce noise.
FUNCTIONAL BLOCK DIAGRAM
5T905 REVISION A 11/3/15
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©2015 Integrated Device Technology, Inc.
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