8T49N287 Datasheet, PDF (64/75 Pages) Integrated Circuit Systems – Optional Fast Lock function

8T49N287 DATA SHEET
Power Dissipation and Thermal Considerations
The 8T49N287 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions
is enabled.
The 8T49N287 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your
own specific configuration.
Power Domains
The 8T49N287 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power
supply pins must still be connected to a valid supply voltage). Figure 14 below indicates the individual domains and the associated power pins.
Output Divider / Buffer Q0 (VCCO0)
Analog & Digital PLL0
(V_CCA & Core V_CC)
Output Divider / Buffer Q1 (VCCO1)
Output Divider / Buffer Q2 (VCCO2)
CLK Input &
Divider Block
(Core V_CC)
Output Divider / Buffer Q3 (V_CCO3)
Output Divider / Buffer Q4 (VCCO4)
Analog & Digital PLL1
(V_CCA & Core V_CC)
Output Divider / Buffer Q5 (VCCO5)
Output Divider / Buffer Q6 (VCCO6)
Output Divider / Buffer Q7 (V_CCO7)
Figure 14. 8T49N287 Power Domains
For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use
a second structure and Q[4:7] use a 3^rd structure. Power consumption data will vary slightly depending on the structure used as shown in the
appropriate tables below.
Power Consumption Calculation
Determining total power consumption involves several steps:
1. Determine the power consumption using maximum current values for core and analog voltage supplies from Table 7A and Table 7B.
2. Determine the nominal power consumption of each enabled output path.
a. This consists of a base amount of power that is independent of operating frequency, as shown in Table 15A through Table 15I
(depending on the chosen output protocol).
b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output
frequency by the FQ_Factor shown in Table 15A through Table 15I.
3. All of the above totals are then summed.
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
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REVISION 5 07/09/15