8T49N287 Datasheet, PDF (21/75 Pages) Integrated Circuit Systems – Optional Fast Lock function

8T49N287 DATA SHEET
Bit Field Name
SLEW0[1:0]
HOLD0[1:0]
HOLDAVG0
FASTLCK0
LOCK0[7:0]
DSM_INT0[8:0]
DSMFRAC0[20:0]
DSM_ORD0[1:0]
DCXOGAIN0[1:0]
DITHGAIN0[2:0]
Rsvd
Digital PLL0 Feedback Configuration Register Block Field Descriptions
Field Type Default Value Description
Phase-slope control for Digital PLL0:
00 = no limit - controlled by loop bandwidth of Digital PLL0 (NOTE 1)
R/W
00b
01 = 83 µsec/sec
10 = 13 µsec/sec
11 = Reserved
Holdover Averaging mode selection for Digital PLL0:
00 = Instantaneous mode - uses historical value 100ms prior to entering holdover
R/W
00b
01 = Fast Average Mode
10 = Reserved
11 = Set VCO control voltage to V_CC/2
Holdover Averaging Enable for Digital PLL0:
R/W
0b
0 = Holdover averaging disabled
1 = Holdover averaging enabled as defined in HOLD0[1:0]
Enables Fast Lock operation for Digital PLL0:
R/W
0b
0 = Normal locking using LCKBW0 & LCKDAMP0 fields in all cases
1 = Fast Lock mode using ACQBW0 & ACQDAMP0 when not phase locked and
LCKBW0 & LCKDAMP0 once phase locked
R/W
3Fh
Lock window size for Digital PLL0. Unsigned 2’s complement binary number in steps
of 2.5ns, giving a total range of 640ns. Do not program to 0.
Integer portion of the Delta-Sigma Modulator value. Do not set higher than FFh. This
R/W
02Dh
implies that for crystal frequencies lower than 16MHz, the doubler circuit must be
enabled.
R/W
000000h
Fractional portion of Delta-Sigma Modulator value. Divide this number by 2²¹ to
determine the actual fraction.
Delta-Sigma Modulator Order for Digital PLL0:
00 = Delta-Sigma Modulator disabled
R/W
11b
01 = 1st order modulation
10 = 2nd order modulation
11 = 3rd order modulation
Multiplier applied to instantaneous frequency error before it is applied to the Digitally
Controlled Oscillator in Digital PLL0:
R/W
01b
00 = 0.5
01 = 1
10 = 2
11 = 4
Dither Gain setting for Digital PLL0:
000 = no dither
001 = Least Significant Bit (LSB) only
010 = 2 LSBs
R/W
000b
011 = 4 LSBs
100 = 8 LSBs
101 = 16 LSBs
110 = 32 LSBs
111 = 64 LSBs
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
NOTE 1: Settings other than “00” may result in a significant increase in initial lock time.
REVISION 5 07/09/15
21
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