IDT82P2821 Datasheet, PDF (61/151 Pages) Integrated Device Technology – 21(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
3.6 CLOCK INPUTS AND OUTPUTS
The IDT82P2821 provides two kinds of clock outputs:
• Free running clock outputs on CLKT1 and CLKE1
• Receiver clock outputs on REFA and REFB
- selected from any of the 22 recovered line clocks
- driven by MCLK (free running)
- driven by external CLKA/CLKB input
A Frequency Synthesizer is also available to scale REFA to 8
different frequencies.
The following Clock Inputs are provided:
• MCLK as programmable reference timing for the IDT82P2821.
• CLKA and CLKB as optional input clock source for REFA and
REFB respectively
3.6.1 FREE RUNNING CLOCK OUTPUTS ON CLKT1/CLKE1
An internal clock generator uses MCLK as reference to generate all
the clocks required by internal circuits and CLKT1/CLKE1 outputs.
MCLK is a stable jitter-free¹ clock input with ±32 ppm (in T1/J1 mode) or
±50 ppm (in E1 mode) accuracy. The clock frequency of MCLK is 1.544/
2.048 X N MHz (1 ≤ N ≤ 8, N is an integer number), as determined by
MCKSEL[3:0]. Refer to Chapter 2 Pin Description for details.
1. Jitter is no more than 0.001 UI.
The outputs on CLKT1 and CLKE1 are free running (locking to
MCLK). The output of CLKT1 is determined by the CLKT1_EN bit (b1,
CLKG) and the CLKT1 bit (b0, CLKG). Refer to Table-23. The output of
CLKE1 is determined by the CLKE1_EN bit (b3, CLKG) and the CLKE1
bit (b2, CLKG). Refer to Table-24.
Table-23 Clock Output on CLKT1
Control Bits
CLKT1_EN
0
1
CLKT1
(don’t-care)
0
1
Clock Output On CLKT1
High-Z
8 KHz
1.544 KHz
Table-24 Clock Output on CLKE1
Control Bits
CLKE1_EN
0
1
CLKE1
(don’t-care)
0
1
Clock Output On CLKE1
High-Z
8 KHz
2.048 KHz
Functional Description
61
January 11, 2007