IDT82P2821 Datasheet, PDF (107/151 Pages) Integrated Device Technology – 21(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2821
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
INTM0 - Interrupt Mask Register 0
Address: 01BH, 05BH, 09BH, 0DBH, 11BH, 15BH, 19BH, 1DBH, (CH1~CH8)
21BH, 25BH, 29BH, 2DBH, 31BH, 35BH, 39BH, 3DBH, (CH9~CH16)
41BH, 45BH, 49BH, 4DBH, 51BH, (CH17~CH21)
7DBH (CH0)
Type: Read / Write
Default Value: FFH
7
6
5
4
DAC_IM
TJA_IM
RJA_IM
TOC_IM
3
TCKLOS_IM
2
TLOS_IM
1
SLOS_IM
0
LLOS_IM
Bit
Name
Description
7
DAC_IM This bit is the waveform amplitude overflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
6
TJA_IM This bit is the TJA FIFO overflow and underflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
5
RJA_IM This bit is the RJA FIFO overflow and underflow interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
4
TOC_IM This bit is the Line Driver TOC interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
3
TCKLOS_IM This bit is the TCLKn missing interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
2
TLOS_IM This bit is the TLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
1
SLOS_IM This bit is the SLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
0
LLOS_IM This bit is the LLOS interrupt mask.
0: Interrupt is enabled.
1: Interrupt is masked. (default)
Programming Information
107
January 11, 2007