IDT72V73273_07 Datasheet, PDF (6/36 Pages) Integrated Device Technology – 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 32,768 X 32,768 CHANNELS

IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
INDUSTRIAL TEMPERATURE RANGE
MICROPROCESSOR INTERFACE
The IDT72V73273’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 16-bit address bus and
a 16-bit data bus all memories can be accessed. Using the TSI microprocessor
interface, reads and writes are mapped into Data and Connection memories.
By allowing the internal memories to be randomly accessed, the controlling
microprocessor has more time to manage other peripheral devices
and can more easily and quickly gather information and setup the switch paths.
Table 1 shows the mapping of the addresses into internal memory blocks. In
order to minimize the amount of memory mapped space however, the Memory
Select (MS1-0) bits in the Control Register must be written to first to select between
the Connection Memory HIGH, the Connection Memory LOW, or Data Memory.
Effectively, the Memory Select bits act as an internal mux to select between the
Data Memory, Connection Memory HIGH, and Connection Memory LOW.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal registers
and memories of the IDT72V73273. The most significant bit of the address select
between the registers and internal memories. See Table 1 for mappings.
As explained in the initialization sections, after system power-up, the TDRSR
and RDRSR, should be programmed immediately to establish the desired
switching configuration.
The data in the Control Register consists of the Software Reset, RX/TX
Bypass, Output Enable Polarity, All Output Enable, Full Block Programming,
Block Programming Data, Begin Block Programming Enable, Reset Connection
Memory LOW in Block Programming, Output Standby, and Memory Select.
SOFTWARE RESET
The Software Reset serves the same function as the hardware reset. As
with the hard reset, the Software Reset must also be set HIGH for 20ns before
bringing the Software Reset LOW again for normal operation. Once the Software
Reset is LOW, internal registers and other memories may be read or written.
During Software Reset, the microprocessor port is still able to read from all
internal memories. The only write operation allowed during a Software Reset
is to the Software Reset bit in the Control Register to complete the Software Reset.
CONNECTION MEMORY CONTROL
If the ODE pin and the Output Standby bit are LOW, all output channels will
be in three-state. See Table 2 for detail.
If MOD2-0 of the Connection Memory HIGH is 1-0-0 accordingly, the output
channel will be in Processor Mode. In this case the lower eight bits of the
Connection Memory LOW are output each frame until the MOD2-0 bits are
changed. If MOD2-0 of the Connection Memory HIGH are 0-0-1 accordingly,
the channel will be in Constant Delay Mode and bits 14-0 are used to address
a location in Data Memory. If MOD2-0 of the Connection Memory HIGH are
0-0-0, the channel will be in Variable Delay Mode and bits 14-0 are used to
address a location in Data Memory. If MOD2-0 of the Connection Memory HIGH
are 1-1-1, the channel will be in High-Impedance mode and that channel will
be in three-state.
RX/TX INTERNAL BYPASS
When the Bypass bit of control registers is 1, all RX streams will be “shorted”
to TX in effect bypassing all internal circuitry of the TSI. This effectively sets the
TSI to a 1-to-1 switch mode with minimal I/O delay. A zero can be written to allow
normal operation. The intention of this mode is to minimize the delay from the RX
input to the TX output making the TSI “invisible”.
INITIALIZATION OF THE IDT72V73273
After power up, the state of the Connection Memory is unknown. As such, the
outputs should be put in High-Impedance by holding the ODE pin LOW. While
the ODE is LOW, the microprocessor can initialize the device by using the Block
Programming feature and program the active paths via the microprocessor bus.
Once the device is configured, the ODE pin (or Output Standby bit depending
on initialization) can be switched to enable the TSI switch.
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